Oxide semiconductors have higher mobility and larger optical band gaps, and can be deposited at lower temperatures, as compared with general amorphous silicon (a-Si). The oxide semiconductors are therefore expected to be applied typically to next-generation displays and to resin substrates, where the next-generation displays require large sizes, high resolutions, and high-speed drive, and the resin substrates have poor heat resistance. For example, an IGZO semiconductor is generally used as the oxide semiconductor. The IGZO semiconductor refers to an amorphous oxide semiconductor including indium, gallium, zinc, and oxygen (In—Ga—Zn—O) (Patent Literature 1).
Demands for still higher mobility have been made more and more on such oxide semiconductors. For example, assume that an oxide semiconductor is allowed to have higher mobility at a level equal to the mobility level (about 40 to about 100 cm2/Vs) of low-temperature poly-silicon (LTPS). In this case, the oxide semiconductor can be used in production of positive channel metal oxide semiconductor (PMOS) transistors and complementary metal oxide semiconductor (CMOS) transistors. Extremely advantageously, this enables, for example, narrower bezel, in which the bezel surrounding a liquid crystal panel is allowed to be narrower, and enables lower cost of the panel.
In addition, TFTs using oxide semiconductors are required to have excellent stress resistance, namely, the TFTs are required to offer a smaller change in threshold voltage between before and after the application of stress, such as the application of a voltage and/or light. For example, it has been pointed out as follows. When a voltage is continuously applied to the gate electrode or when light in the blue band, at which light absorption starts, is continuously applied, charges are trapped at the interface between the gate insulator film and the oxide semiconductor layer in a TFT. This changes the electric charge in the oxide semiconductor layer and thereby significantly shifts the threshold voltage toward a negative side, and this causes the TFT to change in switching behavior. Independently, light leaked out from liquid crystal cells is applied to the TFT upon liquid crystal panel drive or upon lightening of a picture element (pixel) via the application of a negative bias to the gate electrode. This light applies stress to the TFT and causes image irregularities and/or deterioration in TFT characteristics. Upon actual use of the TFT, the change in switching behavior caused by stress due to the application of light or voltage causes deterioration in reliability of the display device itself.
Likewise, organic electroluminescent displays disadvantageously suffer from variations in values typically of threshold voltage, because light leaked out from the light-emitting layer is applied to the semiconductor layer.
As is described above, strong demands are made to improve stress resistance, because the threshold voltage shift, in particular, causes deterioration in reliability of display devices including TFTs. The display devices are exemplified by liquid crystal displays (LCD) and organic electroluminescent displays.
In addition, a thin oxide semiconductor film is exposed to various chemicals (chemical solutions) during preparation of a TFT substrate bearing the thin oxide semiconductor film and source-drain electrodes disposed on or over the thin oxide semiconductor film. Thus, the thin oxide semiconductor film is also required to have resistance to the chemicals. For example, etching via dry etching or wet etching, and photolithography are performed upon formation of the source-drain electrodes on the thin oxide semiconductor film. The wet etching employs a wet etchant. The photolithography employs a resist stripper so as to remove the resist and to clean the work.
For example, assume that a thin oxide semiconductor film and source-drain electrodes are formed via wet etching. In this case, the thin oxide semiconductor film is required to have two properties (A) and (B1) as follows.
(A) The thin oxide semiconductor film is required to have excellent solubility in a wet etchant for oxide semiconductor processing.
Specifically, the thin oxide semiconductor film is required to be etched at an appropriate rate by an organic acid wet etchant such as oxalic acid and to be patterned without residue, where the organic acid wet etchant is used in processing of such thin oxide semiconductor films.
(B1) The thin oxide semiconductor film is required to be insoluble in a wet etchant for source-drain electrodes.
Specifically, another wet etchant is used upon processing of an interconnection film for source-drain electrodes, where the interconnection film is deposited on the thin oxide semiconductor film. This wet etchant is exemplified by inorganic acids including phosphoric acid, nitric acid, and acetic acid. The source-drain electrodes are etched by the wet etchant at an appropriate rate. In this process, the thin oxide semiconductor film is required to resist erosion and damage by the wet etchant on the surface (back channel) side of the thin oxide semiconductor film, where the erosion and damage may cause deterioration in TFT characteristics and stress resistance.
The etching degree (etching rate) by a wet etchant varies also depending on the type of the wet etchant. The IGZO has excellent solubility in organic acid wet etchants such as oxalic acid, but also has high solubility in inorganic acid wet etchants such as phosphoric acid, nitric acid, and acetic acid, and is extremely readily etched by the inorganic acid wet etchants. Specifically, the IGZO is excellent in the property (A), i.e., wet etching characteristics upon thin oxide semiconductor film processing, but is inferior in the property (B1), i.e., durability in wet etching upon source-drain electrodes processing. Disadvantageously, the IGZO film may disappear upon source-drain electrodes processing with the wet etchant to impede the TFT formation or may cause the resulting TFT to have TFT characteristics and other properties at inferior levels. As a possible solution to solve these disadvantages, there has been studied the use of a chemical that does not etch the IGZO, such as a mixture of NH1F and H2O2, as a wet etchant for source-drain electrodes. However, this chemical (wet etchant) has a short lifetime, is unstable, and offers poor mass productivity.
The deterioration in properties such as TFT characteristics with wet etching of the source-drain electrodes, as described in the property (B1), is observed particularly in TFTs having a back channel etch (BCE) structure including no etch stopper layer, as illustrated in FIG. 1.
Specifically, structures of bottom-gate TFTs using oxide semiconductors are roughly classified into a BCE TFT structure and an ESL TFT structure. The “BCE TFT structure” refers to a back-channel etch structure including no etch stopper layer, as illustrated in FIG. 1. The “ESL TFT structure” refers to an etch-stop-layer structure including an etch stopper layer 8, as illustrated in FIG. 2.
The etch stopper layer 8 in the ESL TFT illustrated in FIG. 2 is disposed so as to eliminate or minimize deterioration in transistor characteristics caused by damage of an oxide semiconductor layer 4 upon etching of source-drain electrodes 5. The ESL TFT illustrated in FIG. 2 less suffers from damage to the semiconductor layer surface upon source-drain electrodes processing and readily offers good TFT characteristics. The etch stopper layer is generally selected from insulating films such as SiO2 films.
In contrast to this, the BCE TFT illustrated in FIG. 1 does not include an etch stopper layer and offers excellent productivity, because the number of steps can be reduced to simplify the production process. Specifically, some production methods do not cause damage to the oxide semiconductor layer 4 upon etching, even when no etch stopper layer is provided. For example, when the source-drain electrodes 5 are processed by a lift-off technique, the lift-off technique does not cause damage to the oxide semiconductor layer 4, and this eliminates the need for etch stopper layers. In this case, the BCE TFT illustrated in FIG. 1 is usable. The BCE TFT illustrated in FIG. 1 is also usable upon use of a special wet etchant that is developed so as to allow the TFT to offer good TFT characteristics even when including no etch stopper layer.
From the viewpoints of TFT production cost reduction and process simplification, the BCE TFT illustrated in FIG. 1, which includes no etch stopper layer, is recommended to be used, as described above. However, the above-described disadvantages of the BCE TFT in wet etching are highly feared. Certainly, the ESL TFT illustrated in FIG. 2 may also suffer from the disadvantages caused by wet etchants of some types.
The disadvantages have been described in the property (B1) in the case where the source-drain electrodes are etched via wet etching with a wet etchant. The same disadvantages also occur in the case where the source-chain electrodes are etched via dry etching. The source-drain electrodes are formed via photolithography and etching. In this process, the disadvantages also occur when a resist stripper is used for resist removal and/or for cleaning. The resist striper is exemplified by amine-containing basic aqueous resist strippers, and non-aqueous resist strippers.
Exemplary techniques proposed to restrain damage to the oxide semiconductor layer in the BCE TFT can be found in Patent Literature 2 to 4 below. With these techniques, a sacrificial layer or a cutout is formed between the oxide semiconductor layer and the source-drain electrodes to restrain damage to the oxide semiconductor layer. The formation of the sacrificial layer or cutout, however, requires a larger number of steps. Nonpatent Literature 1 describes the removal of a damaged layer from the oxide semiconductor layer surface. However, it is difficult to uniformly remove the damaged layer.